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Nov. 1999 Ver 2.2
HYUNDAI
GMS81C50 Series
CONTENTS
1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.3 Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3. PIN ASSIGNMENT (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4. PACKAGE DIMENSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . . . . . . 7 4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH) . . . . . . . 7 4.3 40 PDIP Pin Dimension (dimension in inch) . . . . . . . . . . . . . . . . . . . 8 4.4 44 PLCC Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . 8 4.5 44 QFP Pin Dimension (dimension in mm) . . . . . . . . . . . . . . . . . . . . 9 5. PIN FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. PORT STRUCTURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 R1 Ports (R10, R11, R12, R13, R14) . . . . . . . . . . . . . . . . . . . . . . . 12 6.3 R1 Ports (R15, R16, R17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.4 R2, R3, R4 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.5 REMOUT Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.6 Xin, Xout Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7 RESET Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8 TEST Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 Absolute maximum ratings ( Ta=25 'C) . . . . . . . . . . . . . . . . . . . . . 16 7.2 Recommended Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 DC characteristics (VDD=2.2~4.0, Vss=0, Ta=0~70 `C) . . . . . . . . 17 7.4 REMOUT Port Ioh characteristics graph . . . . . . . . . . . . . . . . . . . . 18 7.5 REMOUT port Iol characteristics graph . . . . . . . . . . . . . . . . . . . . . 18 7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70'C) . . . . . . . 19 8. MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.4 Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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9. I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.1 R0 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.2 R1 Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9.3 R2 Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10. CLOCK GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.1 Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 11. TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.1 Basic Interval Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11.2 Timer0, Timer1, Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12. INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.1 Interrupt priority and sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 12.2 INTERRUPT CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . 58 12.3 INTERRUPT ACCEPT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12.4 INTERRUPT PROCESSING SEQUENCE . . . . . . . . . . . . . . . . . . 60 12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction) 61 12.6 MULTIPLE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12.7 Key Scan Input Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13. WATCH DOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.1 Control of WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 13.2 WDT Interrupt Interval . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 14. STANDBY FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.1 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.2 STOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 14.3 STANDBY MODE RELEASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 14.4 RELEASE OPERATION OF STANDBY MODE . . . . . . . . . . . . . . 72 15. OSCILLATION CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 16. RESET FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.1 EXTERNAL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.2 POWER ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 16.3 Low Voltage Detection Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 16.4 Low Voltage Indicator Register (LVIR) . . . . . . . . . . . . . . . . . . . . . 79
HYUNDAI
GMS81C50 Series
GMS81C50 Series
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR UR (Universal Remocon) & KEYBOARD
1. OVERVIEW
1.1 Description
The GMS81C50 Series is an advanced CMOS 8-bit microcontroller with 16K/24K/32K bytes of ROM. The device is one of GMS800 family. The LG Semicon GMS81C50 Series is a powerful microcontroller which provides a highly flexible and cost effective solution to many UR & Keyboard applications. The GMS81C50 Series provides the following standard features: 16K/24K/32K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C50 Series supports power saving modes to reduce power consumption.
1.2 Features
Device Name GMS81C5016 GMS81C5024 GMS81C5032 ROM Size 16K Bytes 24K Bytes 32K Bytes RAM Size 448 Bytes ( included 256 bytes stack memory ) Package 28 SOP 28 Skinny DIP 40 PDIP 44 PLCC 44 QFP
* Instruction Cycle Time: - 1us at 4MHz * Programmable I/O pins
- Watch Dog Timer ............ 6Bit * 1ch * 8 Interrupt sources * Nested Interrupt control is available. - External input: 2 - Keyscan input - Basic Interval Timer - Watchdog timer - Timer : 3 * Power On Reset * Power saving Operation Modes - STOP - SLEEP * Low Voltage Detection Circuit * Watch Dog Timer Auto Start (During 1second after Power on Reset)
28 PIN INPUT OUTPUT I/O 3 2 21
40 PIN 3 2 33
44 PIN 3 2 33
* Operating Voltage - 2.2 ~ 4.0 V @ 4MHz * Timer - Timer / Counter ......... 16 Bit * 1 ch ......... 8 Bit * 2 ch - Basic Interval Timer ...... 8 Bit * 1 ch
1.3 Development Tools
The GMS81C50 Series is supported by a full-featured
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macro assembler, an in-circuit emulator CHOICE-DrTM.
In Circuit Emulators Assembler CHOICE-Dr. (with EVA81C) LGS Macro Assembler
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GMS81C50 Series
2. BLOCK DIAGRAM
G8MC Core
R0 Port
R00 ~ R07
Watchdog Timer REMOUT R17 / T0 R16 / T1 R15 / T2 R14 / EC RAM (448byte) Timer
R1 Port
R10 ~ R17
R2 Port ROM Interrupt (32 Kbyte) Key Scan INT. Generation Block
R20 ~ R27
R12 / INT2 R11 / INT1
R00 ~ R07 R10 ~ R17
R3 Port
R30 ~ R37
TEST RESET XIN XOUT
Clock Gen. & System Control
Prescaler & B.I.T
R4 Port
R40
VDD VSS
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3. PIN ASSIGNMENT (Top View)
R01 R02 R03 R04 R05 R06 R07 VDD XOUT XIN R10 R11/ INT1 R12/ INT2 R13

R00 R24 R23 R22 R21 R20 VSS R17/ T0 R16/ T1 REMOUT R15/ T2 R14/ EC RESET TEST
R00 R01 R02 R03 R04 R05 R06 R07 R34 R35 VDD R36 R37 XOUT XIN R10 R11/ INT1 R12/ INT2 R13 TEST
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32
R27 R26 R25 R24 R23 R22 R21 R20 R33 VSS R32 R31 R30 R17 / T0 R16 / T1 R40 REMOUT R15 / T2 R14 / EC RESET
40PDIP
31 30 29 28 27 26 25 24 23 22 21
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GMS81C50 Series
44
43
42
41
R17 / T0
VSS
VSS
R21
R20
R32
R31
R23 R24 R25 R26 R27 VDD R00 R01 R02 R03 R04
7 8 9 10 11 12 13 14 15 16 17
40
6
5
4
3
2
1
R16 / T1
R22
R33
R30
39 38 37 36 35
R40 REMOUT R15 / T2 R14 / EC RESET VSS TEST R13 R12 / INT2 R11 / INT1 R10
44PLCC
34 33 32 31 30 29
18
19
20
21
22
23
24
25
26
27
R06
R05
R34
R36
R07
R35
R37
5
XOUT
VDD
VDD
XIN
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33
32
31
30
29
28
27
26
25
24
R17 / T0
VSS
VSS
R21
R20
R32
R31
23
R16 / T1
R22
R33
R30
R23 R24 R25 R26 R27 VDD R00 R01 R02 R03 R04
34 35 36 37 38 39 40 41 42 43 44
22 21 20 19 18
R40 REMOUT R15 / T2 R14 / EC RESET VSS TEST R13 R12 / INT2 R11 / INT1 R10
44QFP
17 16 15 14 13 12
10
R05
R06
R34
R36
R07
R35
R37
6
XOUT
VDD
VDD
XIN
11
1
2
3
4
5
6
7
8
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GMS81C50 Series
4. PACKAGE DIMENSION
4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH)
4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH)
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4.3 40 PDIP Pin Dimension (dimension in inch)
2.075 2.045 0.600 BSC 0.550 0.530 0.140 0.120
0.200 max.
MIN 0.015
0.022 0.015
0.065 0.045
0.100 BSC
0.012 0.008
4.4 44 PLCC Pin Dimension (dimension in mm)
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4.5 44 QFP Pin Dimension (dimension in mm)
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5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. TEST: Used for shipping inspection of the IC. For normal operation, it should be connected to VDD. RESET: Reset the MCU. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R1 serves the functions of the various followR20~R22, R30~R37 : R2 & R3 is a 8-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the their Port Direction Register can be used as outputs or inputs. R40 : R40 is 1-bit CMOS bidirectional I/O port. This pin 1 or 0 written to the its Port Direction Register can be used as outputs or inputs. ing special features.
Port pin R11 R12 R14 R15 R16 R17 Alternate function INT1 (External Interrupt input 1) INT2 (External Interrupt input 2) /EC (Event Counter input ) T2 (Timer / Counter input 2) T1 (Timer / Counter input 1) T0 (Timer / Counter input 0)
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PIN NAME R00 R01 R02 R03 R04 R05 R06 R07 R10 R11/INT1 R12/INT2 R13 R14/EC R15/T2 R16/T1 R17/T0 R20 R21 R22 R23 R24 R25 R26 R27 R30 R31 R32 R33 R34 R35 R36 R37 R40 XIN XOUT REMOUT RESET TEST VDD VSS
Pin Numbers INPUT/ OUTPUT 28Pin 40PDIP 44PLCC 44QFP I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O I I P P
28 1 2 3 4 5 6 7 11 12 13 14 17 18 20 21 23 24 25 26 27 10 9 19 16 15 8 22 1 2 3 4 5 6 7 8 16 17 18 19 22 23 26 27 33 34 35 36 37 38 39 40 28 29 30 32 9 10 12 13 25 15 14 24 21 20 11 31 13 14 15 16 17 18 19 20 29 30 31 32 36 37 40 41 4 5 6 7 8 9 10 11 42 43 44 3 21 22 25 26 39 28 27 38 35 33 41 42 43 44 1 2 3 4 12 13 14 15 19 20 23 24 31 32 33 34 35 36 37 38 25 26 27 30 4 5 8 9 22 11 10 21 18 16
Function
@ RESET @ STOP
- Each bit of the port can be individually configured as an input or an output by user software - Push-pull output - CMOS input with pull-up resistor (can be selectable by user software) - Can be programmable as Key Scan Input or Open drain output - Pull-ups are automatically disabled at output mode
INPUT
State of before STOP
- Each bit of the port can be individually configured as an input or an output by user software - CMOS input with pull-up resistor (can be selectable by user software) - Push-pull output - Can be programmable as Open drain output - Direct Driving of LED(N-TR) - Pull-ups are disabled at output mode
- Oscillator Input - Oscillator Output - High Current Output - Includes pull-up resistor - Includes pull-up resistor - Positive power supply - Ground
Low High L output L Output state L level of before STOP
12,23,24 6,7,39
1,2.34 17,28,29
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6. PORT STRUCTURES
6.1 R0 Ports
Pin Name
Open drain Selection Pull-up Selection
Circuit Type
VDD
@ RESET
VDD Data Register
R00 ~ R07
Direction Register
PAD
Hi - Z or High-Input (with pullup)
VSS Data Bus Rd Data Bus Rd MUX
6.2 R1 Ports (R10, R11, R12, R13, R14)
Pin Name
Open drain Selection Pull-up Selection Function Selection
Circuit Type
VDD
@ RESET
VDD
R10 R11 / INT1 R12 / INT2 R13 R14 / EC
Data Register PAD Direction Register
Hi - Z or High-Input (with pullup)
Data Bus
MUX
VSS
Rd to R11...INT1 to R12...INT2 to R14...EC NOISE FILTER
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GMS81C50 Series
6.3 R1 Ports (R15, R16, R17)
Pin Name
Open drain Selection Pull-up Selection Function Selection from R15...T2 from R16...T1 from R17...T0 Data Register Direction Register MUX
Circuit Type
VDD
@ RESET
VDD
R15 / T2 R16 / T1 R17 / T0
PAD
Hi - Z or High-Input (with pullup)
VSS Data Bus MUX
Rd
6.4 R2, R3, R4 Ports
Pin Name
Circuit Type
@ RESET
Open drain Selection Pull-up Selection
VDD
R20 ~ R27 R30 ~ R37 R40
Data Register
VDD
PAD Direction Register
Hi - Z or High-Input (with pullup)
VSS Data Bus Rd MUX
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6.5 REMOUT Port
Pin Name
Circuit Type
VDD
@ RESET
REMOUT
internal signal
PAD
Low level
VSS
6.6 Xin, Xout Ports
Pin Name
Circuit Type
@ RESET
Xout Xin
NOISE FILTER
Xin Xout
oscillation
VSS
from STOP circuit
6.7 RESET Port
Pin Name
Circuit Type
@ RESET
VDD
Pull - up resistor RESET
NOISE FILTER PAD
Low level
from POWER on RESET circuit
VSS
VSS
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GMS81C50 Series
6.8 TEST Port
Pin Name
Circuit Type
@ RESET
VDD
Pull - up resistor TEST
NOISE FILTER PAD
High level
VSS
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute maximum ratings ( Ta=25 'C)
Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation
Symbol VDD VI VO Topr Tstg PD
Rating -0.3 ~ +7.0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 0 ~ 70 -65 ~ 150 700
Unit V V V mW
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
7.2 Recommended Operating Ranges
Parameter Supply Voltage Oscillation Frequency Operating Temperature
Symbol VDD fXin Topr
Condition fXin = 4MHz
min. 2.2 1.0 0
typ.
max. 4.0 4.0 70
Unit V MHz
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GMS81C50 Series
7.3 DC characteristics (VDD=2.2~4.0, Vss=0, Ta=0~70 `C)

! "! #! $$% ! '$ ! "! #(! " )! # ! "! #! $$% ! '$ ! "! #(! " )! # - #! $$% - #! $$% '*. ( '$ &(! " )! # 2 ! "! )! # 2 - # - # $82%! & $82% $$% - # ; ; 7 7 , 7 . 01 , 7 . 1 , 7 . "1 ,7 1 ,7 01 ,7 "1 7 7 7 " 7 7 ) 7 ) 7 #89: 7 #89: ; ; 7 # 7 "" 7 # 7 "" 7 # 7 "
& " )

"
* + * +
"
, ,
. . # . # . < # . . ) 0 0 0 . "
-
1 1 1 1 1 1 1 1 1 1 1 1 1 1

" )
* + * + * .
" ) , , , , , ," ,
.0 ) / / / ) "
) ) # "#
23$ 45 $6%
, ,

&
" ) "
18 ;
17
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7.4 REMOUT Port Ioh characteristics graph
0.0
-5.0 VDD=2V -10.0
-15.0 IOH(mA) VDD=3V -20.0
-25.0
-30.0 VDD=4V -35.0
0 1 2 3 4
VOH(V)
7.5 REMOUT port Iol characteristics graph
8.00 7.00 VDD=4V 6.00 5.00 IOL(mA) 4.00 VDD=3V 3.00 2.00 1.00 0.00
0 1 2 3 4
VDD=2V
VOL(V)
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GMS81C50 Series
7.6 AC characteristics (VDD=2.2~4.0V, Vss=0V, Ta=0~70'C)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13
Parameter External clock input cycle time System clock cycle time External clock pulse width High External clock pulse width Low External clock rising time External clock falling time interrupt pulse width High Interrupt pulse width Low Reset input pulse width low Event counter input pulse width high Event counter input pulse width low Event counter input pulse rising time Event counter input pulse falling time
Symbol tcp tsys tcpH tcpL trcp tfcp tIH tIL tRSTL tECH tECL trEC tfEC
Pin min. Xin 250 500 Xin Xin Xin Xin INT1~ INT2 INT1~ INT2 RESET EC EC EC EC 2 2 8 2 2 40 40
Specification typ. 500 1000 max. 1000 2000
Unit ns ns ns ns 40 40 ns ns tsys tsys tsys tsys tsys 40 40 ns ns
(Continued)
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GMS81C50 Series
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tCP
tCPH
tCPL Vcc-0.5V
XIN
0.5V trCP tIH tfCP tIL 0.8Vcc
INT1 INT2
0.2Vcc
tRSTL
RESET
0.2Vcc
tECL
tECH 0.8Vcc
EC
0.2Vcc trEC tfEC
Figure 7-1 Clock, Interrupt, RESET, EC Input Timing
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8. MEMORY ORGANIZATION
The GMS81C50 Series has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 32K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area.
8.1 Registers
This device has six registers that are the Program Counter (PC), an Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. * X Register : In the case of division instruction, execute as register. * Y Register : In the case of 16-bit operation instruction, execute as the upper 8-bit of YA. (16-bit accumulator). In the case of multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8bit of the result enters. In the case of division instruction, execute as the upper 8-bit of dividend. After division operation, remains enters. Y register can be used as loop counter of conditional branch command. (e.g.DBNE Y, rel) Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts, calling out subroutines and PUSH, POP, RETI, RET instruction. Stack Pointer identifies the location in the stack to be accessed (save or restore). Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted. The SP is pre-incremented when a return or a pop instruction is executed. The stack can be located at any position within 100H to 1FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH" is
Figure 8-1 Configuration of Registers
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below. In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8bit of the result enters. (Y*A => YA). In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters.
Y
Y A
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
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used.
Stack Address ( 100H ~ 1FFH ) 15 1 8 7 SP 0
Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP
Hardware fixed
LDX TXSP
#0FFH
; SP FFH
At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RETI instruction
01FC 01FD 01FE 01FF PCL PCH Push down
01FC 01FD 01FE 01FF PSW PCL PCH Push down
01FC 01FD 01FE 01FF PCL PCH Pop up
01FC 01FD 01FE 01FF PSW PCL PCH Pop up
SP before execution SP after execution
01FF 01FD
01FF 01FC
01FD 01FF
01FC 01FF
At execution of PUSH instruction PUSH A (X,Y,PSW) 01FC 01FD 01FE 01FF A Push down
At execution of POP instruction POP A (X,Y,PSW) 01FC 01FD 01FE 01FF A Pop up 01FFH 0100H
Stack depth
SP before execution SP after execution
01FF 01FE
01FE 01FF
Figure 8-3 Stack Operation
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that
reflect the current state of the CPU. The PSW is described in Figure 8-4 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
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[Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result.
MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR BRK FLAG
LSB
N
V
G
B
H
I
Z
C
RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-4 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G] This flag assigns RAM page for direct addressing mode. In
the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is 1 Page. It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH) or -128(80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 16K/24K/32K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6 . As shown in Figure 8-5 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 0FH : : ;1BYTE INSTR UCTIO N ;INSTEAD OF 2 BYTES ;NOR M AL C ALL
8000H 32KByte Range A000H 24KByte Range C000H 16KByte Range FF00H FFC0H FFE0H FFFFH PCALL AREA TCALL AREA INTERRUPT VECTOR AREA U-PAGE PROGRAM MEMORY
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Address Vector Area Memory S/W Interrupt Vector Area Basic Interval Timer Interrupt Vector Area Watch Dog Timer Interrupt Vector Area Timer2 Interrupt Vector Area Timer1 Interrupt Vector Area Timer0 Interrupt Vector Area External Interrupt 2 Vector Area External Interrupt 1 Vector Area Key Scan Interrupt Vector Area RESET Vector Area
Figure 8-5 Program Memory Map
0FFDEH E0 E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7 .
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (192 Bytes)
0FFBFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
0D125H NEXT
~ ~
Reverse
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH DH 6H
0FF00H 0FFD6H 25 D1
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED NOT_USED NOT_USED BIT_INT WDT_INT NOT_USED NOT_USED TMR2_INT TMR1_INT TMR0_INT NOT_USED INT2 INT1 KEY_INT NOT_USED RESET 08000H
; BIT ; Watch Dog Timer ; ; ; ; ; ; ; ; ; Timer-2 Timer-1 Timer-0 Int.2 Int.1 Key Scan Reset
;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; ; LDX #03FH ;Stack Pointer Initialize TXSP LDM LDM LDM LDM : : LDM : : R0, #0 R0DD,#1000_0010B PUR0,#1000_0010B PMR0,#0000_0001B PCOR,#1 ;Normal Port 0 ;Normal Port Direction ;Pull Up Selection Set ;R0 port / int ;Enable Peripheral clock
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8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into 3 groups, a user RAM, control registers, Stack.
0000H
Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section.
RAM (192 Bytes) PAGE0 00BFH 00C0H 00FFH 0100H RAM (STACK) (256 Bytes) PAGE1 CONTROL REGISTERS
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
Example; To write at CKCTLR
LDM CLCTLR,#09H ;Divide ratio /8
01FFH
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-3 on page 22.
Figure 8-8 Data Memory Map
User Memory The GMS81C50 Series has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH.
Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h
Function Register PORT R0 DATA REG. PORT R0 DATA DIRECTION REG. PORT R1 DATA REG. PORT R1 DATA DIRECTION REG. PORT R2 DATA REG. PORT R2 DATA DIRECTION REG. reserved
Read Write R/W W R/W W R/W W
Symbol R0 R0DD R1 R1DD R2 R2DD
RESET Value undefined 00000000b undefined 00000000b undefined 00000000b
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00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h
CLOCK CONTROL REG. BASIC INTERVAL REG. WATCH DOG TIMER REG. PORT R1 MODE REG. INT. MODE REG. EXT. INT. EDGE SELECTION INT. ENABLE REG. LOW INT. REQUEST FLAG REG. LOW INT. ENABLE REG. HIGH INT. REQUEST FLAG REG. HIGH TIMER0 (16bit) MODE REG. TIMER1 (8bit) MODE REG. TIMER2 (8bit) MODE REG. TIMER0 HIGH-MSB DATA REG. TIMER0 HIGH-LSB DATA REG. TIMER0 LOW-MSB DATA REG. TIMER0 HIGH-MSB COUNT REG. TIMER0 LOW-LSB DATA REG.
W R W W R/W W R/W R/W R/W R/W R/W R/W R/W W W W R W W W W R W R R/W
CKCTLR BTR WDTR PMR1 IMOD IEDS IENL IRQL IENH IRQH TM0 TM1 TM2 T0HMD T0HLD T0LMD
--110111b undefined -0001111b 00000000b -0000000b 00000000b -00-----b -00-----b 000-000-b 000-000-b 00000000b 00000000b 00000000b undefined undefined undefined undefined
T0LLD
undefined undefined
00D6h TIMER0 LOW-LSB COUNT REG. 00D7h 00D8h TIMER1 LOW COUNT REG. TIMER2 DATA REG. 00D9h TIMER2 COUNT REG. 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h TIMER0 / TIMER1 MODE REG. Reserved STANDBY MODE RELEASE REG0 STANDBY MODE RELEASE REG0 PORT R1 OPEN DRAIN ASSIGN REG. PORT R2 OPEN DRAIN ASSIGN REG. PORT R3 OPEN DRAIN ASSIGN REG. PORT R4 OPEN DRAIN ASSIGN REG. Reserved Reserved PORT R0 OPEN DRAIN ASSIGN REG. PORT R3 DATA REG. PORT R3 DATA DIRECTION REG. W R/W W R0ODC R3 R3DD 00000000b undefined 00000000b W W W W W W SMPR0 SMPR1 R1ODC R2ODC R3ODC R4ODC 00000000b 00000000b 00000000b 00000000b 00000000b - - - - - - - 0b undefined TM01 00000000b undefined T2DR undefined TIMER1 HIGH DATA REG. TIMER1 LOW DATA REG. T1HD T1LD undefined undefined
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00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh
PORT R4 DATA REG. PORT R4 DATA DIRECTION REG. Reserved Reserved Reserved Reserved Reserved Reserved LOW VOLTAGE INDICATION REG. SLEEP MODE REG. Reserved Reserved Reserved Reserved Reserved STANDBY RELEASE LEVEL CONT. REG. 0 STANDBY RELEASE LEVEL CONT. REG. 1 PORT R0 PULL-UP REG. CONT. REG. PORT R1 PULL-UP REG. CONT. REG. PORT R2 PULL-UP REG. CONT. REG. PORT R3 PULL-UP REG. CONT. REG. PORT R4 PULL-UP REG. CONT. REG. Reserved Reserved Reserved
R/W W
R4 R4DD
- - - - - - - Xb - - - - - - - 0b
R W
LVIR SLPM
- - - - - - 00b - - - - - - - 0b
W W W W W W W
SRLC0 SRLC1 R0PC R1PC R2PC R3PC R4PC
00000000b 00000000b 00000000b 00000000b 00000000b 00000000b - - - - - - - 0b
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8.4 Addressing Mode
The GMS81C50 Series uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
35H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0
C535 LDA 35H ;A RAM[35H]
~ ~
~ ~
data A
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
0435 ADC #35H
MEMORY
0E550H 0E551H
C5 35
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
0735F0 ADC !0F035H ;A ROM[0F035H]
04 35
A+35H+C A
When G-flag is 1, then RAM address is difined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=0CH
E45535 LDM 35H,#55H ~ ~
0F100H 0F101H 0C35H data data 55H 0F102H 07 35 F0 0F035H data
~ ~
A+data+C A
address: 0F035
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
983501 INC !0135H ;A ROM[135H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
DB LDA {X}+
135H
data
~ ~
~ ~
0F100H 0F101H 0F102H 98 35 01

data+1 data
35H
data
~ ~
data A
~ ~
DB
address: 0135
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H
D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
C645 LDA 45H+X
115H
data
~ ~
data A
~ ~
0E550H D4
3AH
data
~ ~
0E550H 0E551H C6 45
~ ~

data A
45H+0F5H=13AH
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
D500FA LDA !0FA00H+Y
3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
1625 ADC [25H+X]
~ ~
0FA55H data
~ ~

data A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~ 0E005H ~
25 + X(10) = 35H
~ ~
~ ~
16 25
A + data + C A
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Y indexed indirect [dp]+Y Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
1F25E0 JMP [!0C025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
0E005H + Y(10) = 0E015H
~ ~
~ ~
NEXT
jump to address 0E30AH
~ ~
0E725H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25 E0
~ ~
A + data + C A
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9. I/O PORTS
The GMS81C50 Series has 33 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O), PORT2 (8 I/O), PORT3 (8 I/O), PORT4 (1 I/O). Pull-up resistor of each port can be selectable by program. Each port contains data direction register which controls I/O and data register which stores port data. (1) R0 I/O Data Direction Register (R0DD) R0 I/O Data Direction Register (R0DD) is 8-bit register, and can assign input state or output state to each bit. If R0DD is 1, port R0 is in the output state, and if 0, it is in the input state. R0DD is write-only register. Since R0DD is initialized as 00 h in reset state, the whole port R0 becomes input state. (2) R0 Data Register (R0) R0 data register (R0) is 8-bit register to store data of port R0. When set as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0 is unknown in reset state. (3) R0 Open drain Assign Register (R0ODC) R0 Open Drain Assign Register (R0ODC) is 8bit register, and can assign R0 port as open drain output port each bit, if corresponding port is selected as output. If R0ODC is selected as 1, port R0 is open drain output, and if selected as 0, it is push-pull output. R0ODC is write-only register and initialized as 00 h in reset state. (4) R0 Pull-up Resistor Control Register (R0PC) R0 pull-up resistor control register (R0PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R0PC is selected as 1, pullup ia disabled and if selected as 0, it is enabled. R0PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
9.1 R0 Ports
R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DD register (address 0C1H). R0 has internal pull-ups that is independently connected or disconnected by R0PC. The control registers for R0 are shown below.
R0 Data Register (R/W) R0
ADDRESS : 0C0H RESET VALUE : Undefined
R07 R06 R05 R04 R03 R02 R01 R00
R0 Direction Register (W) R0DD
ADDRESS : 0C1H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS :0F8H RESET VALUE : 00H
R0 Pull-up Selection Register (W) R0PC
Pull-up select 0: Without pull-up 1: With pull-up
R0 Open drain Assign Register (W) ADDRESS :0E4H RESET VALUE : 00H R0ODC Open drain select 0: Push-pull 1: Open drain
9.2 R1 Ports
R1 is an 8-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R1DD register (address 0C3H). R1 has internal pull-ups that is independently connected or disconnected by register R1PC. The control registers for R1 are shown below.
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(3) R1 Mode Register (PMR1)
R1 Data Register (R/W) R1 ADDRESS : 0C2H RESET VALUE : Undefined
R17 R16 R15 R14 R13 R12 R11 R10
R1 Port Mode Register (PMR1) is 8-bit register, and can assign the selection mode for each bit. When set as 0, corresponding bit of PMR1 acts as port R1 selection mode, and when set as 1, it becomes function selection mode. PMR1 is write-only register and initialized as 00 h in reset state. Therefore, becomes Port selection mode. Port R1 can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as 0.
R1 Direction Register (W) R1DD
ADDRESS : 0C3H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS : 0F9H RESET VALUE : 00H
R1 Pull-up Selection Register (W) R1PC
Pin Name
Pull-up select 0: Without pull-up 1: With pull-up
PMR1 0
Selection Mode R17 (I/O) T0 (O) R16 (I/O) T1 (O) R15 (I/O) T2 (O) R14 (I/O) /EC (I)
Remarks Timer0 Timer1 Timer2 Timer0 Event
T0S 1 0 T1S 1 0 T2S 1 0 ECS 1
R1 Open drain Assign Register (W) ADDRESS : 0DEH RESET VALUE : 00H P1ODC Open drain select 0: Push-pull 1: Open drain
R1 Port Mode Register (W) PMR1
ADDRESS : 0C9H RESET VALUE : 00H
Mode select 0: Port R1 selection 1: Function selection
0 INT2S 1 0 INT1S
R12 (I/O) INT2 (I) R11 (I/O) INT1 (I) Timer0 Input Capture
(1) R1 I/O Data Direction Register (R1DD) R1 I/O Data Direction Register (R1DD) is 8-bit register, and can assign input state or output state to each bit. If R1DD is 1, port R1 is in the output state, and if 0, it is in the input state. R1DD is write-only register. Since R1DD is initialized as 00 h in reset state, the whole port R1 becomes input state. (2) R1 Data Register (R1) R1 data register (R1) is 8-bit register to store data of port R1. When set as the output state by R1DD, and data is written in R1, data is outputted into R1 pin. When set as the input state, input state of pin is read. The initial value of R1 is unknown in reset state.
1
Table 9-1 Selection mode of PMR1
(4) R1 Pull-up Resistor Control Register (R1PC) R1 pull-up resistor control register (R1PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R1PC is selected as 1, pullup ia disabled and if selected as 0, it is enabled. R1PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
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9.3 R2 Port
R2 is an 8-bit CMOS bidirectional I/O port (address 0C4H). Each I/O pin can independently used as an input or an output through the R2DD register (address 0C5H). R2 has internal pujll-ups that is independently connected or disconnected by R2PC (address 0FAH). The control registers for R2 are shown as below.
(1) R2 I/O Data Direction Register (R2DD) R2 I/O Data Direction Register (R2DD) is 8-bit register, and can assign input state or output state to each bit. If R2DD is 1, port R2 is in the output state, and if 0, it is in the input state. R2DD is write-only register. Since R2DD is initialized as 00 h in reset state, the whole port R2 becomes input state. (2) R2 Data Register (R2) R2 data register (R2) is 8-bit register to store data of port R2. When set as the output state by R2DD, and data is written in R2, data is outputted into R2 pin. When set as the input state, input state of pin is read. The initial value of R2 is unknown in reset state. (3) R2 Open drain Assign Register (R2ODC) R2 Open Drain Assign Register (R2ODC) is 8bit register, and can assign R2 port as open drain output port each bit, if corresponding port is selected as output. If R2ODC is selected as 1, port R2 is open drain output, and if selected as 0, it is push-pull output. R2ODC is write-only register and initialized as 00 h in reset state. (4) R2 Pull-up Resistor Control Register (R2PC) R2 pull-up resistor control register (R2PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R2PC is selected as 1, pullup ia disabled and if selected as 0, it is enabled. R2PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
R2 Data Register (R/W) R2
ADDRESS : 0C4H RESET VALUE : Undefined
R27 R26 R25 R24 R23 R22 R21 R20
R2 Direction Register (W) R2DD
ADDRESS : 0C5H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS :0FAH RESET VALUE : 00H
R2 Pull-up Selection Register (W) R2PC
Pull-up select 0: Without pull-up 1: With pull-up
R2 Open drain Assign Register (W) ADDRESS :0DFH RESET VALUE : 00H R2ODC Open drain select 0: Push-pull 1: Open drain
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R3 Port R3 is an 8-bit CMOS bidirectional I/O port (address 0E5H). Each I/O pin can independently used as an input or an output through the R3DD register (address 0E6H). R3 has internal pull-ups that is independently connected or disconnected by R3PC (address 0FBH). The control registers for R3 are shown as below.
(1) R3 I/O Data Direction Register (R3DD) R3 I/O Data Direction Register (R3DD) is 8-bit register, and can assign input state or output state to each bit. If R3DD is 1, port R3 is in the output state, and if 0, it is in the input state. R3DD is write-only register. Since R3DD is initialized as 00 h in reset state, the whole port R3 becomes input state. (2) R3 Data Register (R3) R3 data register (R3) is 8-bit register to store data of port R3. When set as the output state by R3DD, and data is written in R3, data is outputted into R3 pin. When set as the input state, input state of pin is read. The initial value of R3 is unknown in reset state. (3) R3 Open drain Assign Register (R3ODC) R3 Open Drain Assign Register (R3ODC) is 8bit register, and can assign R3 port as open drain output port each bit, if corresponding port is selected as output. If R3ODC is selected as 1, port R3 is open drain output, and if selected as 0, it is push-pull output. R3ODC is write-only register and initialized as 00 h in reset state. (4) R3 Pull-up Resistor Control Register (R3PC) R3 pull-up resistor control register (R3PC) is 8-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R3PC is selected as 1, pullup ia disabled and if selected as 0, it is enabled. R3PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
R3 Data Register (R/W) R3
ADDRESS : 0E5H RESET VALUE : Undefined
R37 R36 R35 R34 R33 R32 R31 R30
R3 Direction Register (W) R3DD
ADDRESS : 0E6H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS :0FBH RESET VALUE : 00H
R3 Pull-up Selection Register (W) R3PC
Pull-up select 0: Without pull-up 1: With pull-up
R3 Open drain Assign Register (W) ADDRESS :0E0H RESET VALUE : 00H R3ODC Open drain select 0: Push-pull 1: Open drain
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R4 Port R4 is an 1-bit CMOS bidirectional I/O port (address 0E7H). Each I/O pin can independently used as an input or an output through the R4DD register (address 0E8H). R3 has internal pull-ups that is independently connected or disconnected by R4PC (address 0FCH). The control registers for R4 are shown as below.
(1) R4 I/O Data Direction Register (R4DD) R4 I/O Data Direction Register (R4DD) is 1-bit register, and can assign input state or output state to each bit. If R4DD is 1, port R4 is in the output state, and if 0, it is in the input state. R4DD is write-only register. Since R4DD is initialized as 00 h in reset state, the whole port R4 becomes input state. (2) R4 Data Register (R4) R4 data register (R4) is 1-bit register to store data of port R4. When set as the output state by R4DD, and data is written in R4, data is outputted into R4 pin. When set as the input state, input state of pin is read. The initial value of R4 is unknown in reset state. (3) R4 Open drain Assign Register (R4ODC) R4 Open Drain Assign Register (R4ODC) is 1-bit register, and can assign R4 port as open drain output port each bit, if corresponding port is selected as output. If R4ODC is selected as 1, port R4 is open drain output, and if selected as 0, it is push-pull output. R4ODC is write-only register and initialized as 00 h in reset state. (4) R4 Pull-up Resistor Control Register (R4PC) R4 pull-up resistor control register (R4PC) is 1-bit register and can control pull-up on or off each bit, if corresponding port is selected as input. If R4PC is selected as 1, pullup ia disabled and if selected as 0, it is enabled. R4PC is write-only register and initialized as 00 h in reset state. The pull-up is automatically disabled, if corresponding port is selected as output.
R4 Data Register (R/W) R4
ADDRESS : 0E7H RESET VALUE : Undefined R40
R4 Direction Register (W) R4DD
ADDRESS : 0E8H RESET VALUE : 00H
Port Direction 0: Input 1: Output ADDRESS :0FCH RESET VALUE : 00H
R4 Pull-up Selection Register (W) R4PC
Pull-up select 0: Without pull-up 1: With pull-up
R4 Open drain Assign Register (W) ADDRESS :0E1H RESET VALUE : 00H R4ODC Open drain select 0: Push-pull 1: Open drain
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10. CLOCK GENERATOR
Clock generating circuit consists of Clock Pulse Generator (C.P.G), Prescaler, Basic Interval Timer (B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock.
fex OSC Circuit C.P.G
fcpu
Internal System Clock
PRESCALER IFBIT PS1 ENPCK 8 MUX B.I.T (8) WDT (6) 9 0 7 0 5 WDTCL
BTCL IFWDT 3 Peripheral COMPARATOR WDTON 6 0 1 2 3 4 5 0 Internal Data Bus WDTR 5 6 6 To Reset Circuit
CKCTLR
Figure 10-1 Block Diagram of Clock Generator
Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex).
The divided output from each bit of prescaler is provided to peripheral hardware.
fex
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T fcpu PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 Peripheral
Figure 10-2 Block diagram of Prescaler
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fex (MHz) ps 0 ps 1 ps 2 ps 3 ps 4 ps 5 ps 6 ps 7 ps 8 ps 9 ps 10 ps 11 ps 12
4 MHz frequency 4 MHz 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz period 250 ns 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us frequency 2 MHz 1 MHz 500 KHz 250 KHz 125 KHz 62.5 KHz 31.25 KHz 15.63 KHz 7.183 KHz 3.906 KHz 1.953 KHz 0.976 KHz 0.488 KHz
2 MHz period 500 ns 1 us 2 us 4 us 8 us 16 us 32 us 64 us 128 us 256 us 512 us 1024 us 2048 us
Table 10-1 ps output period
Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to 1 in reset
state.
7 CKCTLR
Clock Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7 h>
-
ENPCK 0 1
Periphral clock stopped provided
Figure 10-3 Clock Control Register
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10.1 Operation Mode
The system clock controller starts or stops the main-frequency clock oscillator. Figure 10-2 shows the operating mode transition diagram. Main-clock operating mode This mode is fast-frequency operating mode. The CPU and the peripheral hardwares are operated on the high-frequency clock. At reset release, this mode is invoked. STOP mode In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level
Main - Oscillating
Main Operating Mode
NOTE: Refer to 14.3 context
io n
Re
ru ct
e st gi
In st
rs
O P
g tin et
ST
no te
R e ef o rt
er
to
N
Re f
e ot
Instruction
Release
STOP Mode
Reset
Reset
RESET Operation
SLEEP Mode
Main: Stopped
Main: Oscillating
Figure 10-4 Operating Mode
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11. TIMER
11.1 Basic Interval Timer
The GMS81C50 Series has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1 . The Basic Interval Timer generates the time base for key scanning, watchdog timer counting, and etc. It also provides a Basic interval timer interrupt (IFBIT). As the count overflow from FFH to 00H, this overflow causes the interrupt to be generated. -8bit binary counter -Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on -Secures the oscillation stabilization time in standby mode (stop mode) release -Contents of B.I.T can be read -Provides the clock for watch dog timer.
DATA BUS
-
-
WDTON
ENPCK
BTCL
BTS2
BTS1
BTS0
CKCTLR
PS3 PS4 PS5 PS6 MUX PS7 PS8 PS9 PS10 DATA BUS BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
BITR BIT7 IFBIT
Figure 11-1 Block Diagram of Basic Interval Timer
(1) Control of B.I.T The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2 . If bit3(BTCL) of CKCTLR is set to 1, B.I.T is cleared, and then, after one machine cycle, BTCL becomes 0, and B.I.T starts counting. BTCL is set to 0 in reset state.
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7 CKCTLR
Clock Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7 h>
-
BTCL 0 1
Periphral clock free-run Automatically cleared, after one cycle
Figure 11-2 BTCL mode of B.I.T
(2) Input clock selection of B.I.T The input clock of B.I.T can be selected from the prescaler within a range of 2us to 256us by clock input selection bits (BTS2~BTS0). (at fex = 4MHz). In reset state, or power on reset, BTS2=1, BTS1=1, BTS0=1 to secure the longest oscillation stabilization time. B.I.T can generate the wide range of basic interval time interrupt request (IFBIT) by selecting prescaler output. Interrupt interval can be selected to kinds of interval time as shown in Figure 11-3 .
7 CKCTLR
Clock Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7 h>
-
BTS2 0 0 0 0 1 1 1 1
BTS1 0 0 1 1 0 0 1 1
BTS0 0 1 0 1 0 1 0 1
B.I.T. Input clock PS3 (2us) PS4 (4us) PS5 (8us) PS6 (16us) PS7 (32us) PS8 (64us) PS9 (128us) PS10 (256us)
Standby release time 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us
Figure 11-3 Basic Interval Timer Interrupt Time
(3) Reading Basic Interval Timer By reading of the Basic Interval Timer Register (BITR), we can read counter value of B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms can be available. B.I.T is read-only register. If B.I.T reg-
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ister is written, then CKCTLR register with same address
is written.
7 BITR BIT7 BIT6
Basic Interval Timer Register
BIT5 BIT4 BIT3 BIT2 BIT1
0 BIT0 R <00C7 h>
11.2 Timer0, Timer1, Timer2
(1) Timer Operation Mode Timer consists of 16bit binary counter Timer0 (T0), 8bit binary Timer1 (T1), Timer2 (T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 HighMSB Data Register (T0HMD), Timer0 High-LSB Data Register (T0HLD), Timer0 Low-MSB Data Register (T0LMD), Timer0 Low-LSB Data Register (T0LLD), Timer1 High Data Register (T1HD), Timer1 Low Data Register (T1LD), Timer2 Data Register (T2DR). Any of the PS0 ~ PS5, PS11 and external event input EC can be selected as clock source for T0. Any of the PS0 ~ PS3, PS7 ~ PS10 can be selected as clock T1. Any of the PS5 ~ PS12 can be selected as clock source for T2. * Relevant Port Mode Register (PMR1 : 00C9 h) value should be assigned for event counter,
Timer0
- 16-bit Interval Timer - 16-bit Event Counter - 16-bit Input Capture - 16-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - 8-bit Interval Timer - 8-bit rectangular-wave output - Modulo-N Mode
- Single/Modulo-N Mode - Timer Output Initial Value Setting - Timer0~Timer1 combination Logic Output - One Interrupt Generating Every 2nd Counter Overflow
Timer1
Timer2
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EC / R14
TIMER0 (16 BIT)
Polarity Selection
T0 OUT / R17
INT2 / R12 (Capture Signal)
EDGE Selection
16
16
8 T0HMD T0HLD
8
8 T0LMD T0LLD
8
T1HD 8
T1LD Tout LOGIC 8 REMOUT
TIMER1 (8 BIT)
T1 OUT / R16
TIMER2 (8 BIT)
T2 OUT / R15
T2DR
Figure 11-4 Timer / Counter Block diagram
(2) Function of Timer & Counter
fex = 4MHz
16bit Timer (T0) Resolution (CK) PS0 ( 0.25 us) PS1 ( 0. 5 us) PS2 ( PS3 ( PS4 ( PS5 ( 1 us) 2 us) 4 us) 8 us) Max. Count 16,384 us 32,768 us 65,536 us 131,072 us 262,144 us 524,288 us 33,554,432 us 8bit Timer (T1) Resolution (CK) PS0 ( 0.25 us) PS1 ( PS2 ( PS3 ( PS7 ( PS8 ( 0.5 us) 1 us) 2 us) 32 us) 64 us) Max. Count 64 us 128 us 256 us 512us 8,192 us 16,384 us 32,768 us 65,536 us 8bit Timer (T2) Resolution (CK) PS5 ( PS6 ( PS7 ( PS8 ( 8 us) 16 us) 32 us) 64 us) Max. Count 2.048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us 131,072 us 262,144 us
PS9 ( 128 us) PS10 ( 256 us) PS11 ( 512 us) PS12 (1,024 us)
PS11 ( 512 us) EC
PS9 ( 128 us) PS10 ( 256 us)
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Internal Data Bus R/W <00D0 h> TM0 7 6 5 4 3 2 1 0
<00D5 h> <00D6 h> <00D3 h> TIMER0 HM DATA REG <00D4 h> <00D5 h> TIMER0 LM DATA REG <00D6 h>
TIMER0 H COUNT REG
TIMER0 L COUNT REG
TIMER0 HL DATA REG
TIMER0 LL DATA REG
DATA READ
SINGLE/ MODULO-N SELECTION
16
16
MUX
16
PS0 PS1 PS2 PS3 PS4 PS5 PS11 EC D E L A INT2 EDGE SELECTION Y M U X MUX CK Int. Gen. T0 COUNTER (16 BIT) IFT0 Clear
T0INT OUTPUT GEN.
T0 OUT
Figure 11-5 Block Diagram of Timer0
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Internal Data Bus <00D8 h> <00D1h> TM1 7 6 5 4 3 X 2 1 0 R/W TIMER1 COUNT REG TIMER1 H DATA REG TIMER1 L DATA REG <00D7 h> <00D8 h>
SINGLE/ MODULO-N SELECTION
OUTPUT GEN.
PS0 PS1 PS2 PS3 PS7 PS8 PS9 PS10 IFT1 MUX CK T1 COUNTER (8 BIT) Int. Gen.
T1INT
OUTPUT GEN.
T1OUT
Figure 11-6 Block Diagram of Timer1
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Internal Data Bus <00D9 h> <00D2 h> TM2 7 6 5 4 3 2 1 0 R/W TIMER2 COUNT REG TIMER2 DATA REG <00D9 h>
PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 OUTPUT GEN. T2 OUT MUX CK T2 COUNTER (8 BIT) IFT2
Figure 11-7 Block Diagram of Timer2
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7 TM01 TOUTS TOUTB
Timer0 / Timer1 Mode Register
T0OUTP T0INIT T1INIT TOUT1
0 TOUT0 R / W <00DA h>
TOUT0 0 0 1 1 T1INIT 0 1 T0INIT 0 1 T0OUTP 0 1 TOUTB 0 1
TOUT1 0 1 0 1
TOUT LOGIC AND of T0 OUTPUT and T1 OUTPUT NAND of T0 OUTPUT and T1 OUTPUT OR of T0 OUTPUT and T1 OUTPUT NOR of T0 OUTPUT and T1 OUTPUT Timer1 Output Initial Value
Timer1 output low Timer1 output high Timer0 Output Initial Value Timer0 Output Low Timer0 Output High T0OUT Polarity Selection T0OUT polarity equal to TOUT logic input signal T0OUT polarity reverse to TOUT logic input signal REMOUT Port Bit Control REMOUT output low REMOUT output high REMOUT Port Output Selection (TOUT logic or TOUTB) Bit (TOUTB) output through REMOUT TOUT logic output through REMOUT
TOUTS 0 1
Figure 11-8 Timer0 / Timer1 Mode Register
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7 TM0 CAP0 T0ST
Timer0 Mode Register
T0CN T0MOD T0IFS T0SL2 T0SL1
0 T0SL0 R / W <00D0 h>
T0SL2 0 0 0 0 1 1 1 1 T0IFS 0 1 T0MOD 0 1 T0CN 0 1 T0ST 0 1 CAP0 0 1
T0SL1 0 0 1 1 0 0 1 1
T0SL0 0 1 0 1 0 1 0 1
Input clock selection PS0 (250ns) PS1 (500ns) PS2 ( PS3 ( PS4 ( PS5 ( 1us) 2us) 4us) 8us) *
Notes
PS11 (512us) EC
Event Counter
Timer0 Interrupt Selection Interrupt every counter overflow Interrupt every 2nd counter overflow Timer0 Single/Modulo-N Selection Modulo-N Single Timer0 Counter Continuation/Pause Control Count pause Count contination Timer0 Start/Stop Control Timer0 Stop Timer Start after clear Timer0 Interrupt Selection Timer/Counter Input capture *
* PS1 : not supporting input capture.
Figure 11-9 Timer0 Mode Register
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7 TM1 T1ST T1CN
Timer1 Mode Register
T1MOD T1IFS T1SL2 T1SL1
0 T1SL0 R / W <00D1 h>
T1SL2 0 0 0 0 1 1 1 1 T1IFS 0 1 T1MOD 0 1 T1CN 0 1 T1ST 0 1
T1SL1 0 0 1 1 0 0 1 1
T1SL0 0 1 0 1 0 1 0 1
Input clock selection PS0 (250ns) PS1 (500ns) PS2 ( PS3 ( 1us) 2us)
PS7 ( 32us) PS8 ( 64us) PS9 (128us) PS10 (256us)
Timer1 Interrupt Selection Interrupt every counter overflow Interrupt every 2nd counter overflow Timer1 Single/Modulo-N Selection Modulo-N Single Timer1 Counter Continuation/Pause Control Count pause Count contination Timer1 Start/Stop Control Timer1 Stop Timer1 Start after clear
Figure 11-10 Timer1 Mode Register
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7 TM2 -
Timer2 Mode Register
T2ST T2CN T2SL2 T2SL1
0 T2SL0 R / W <00D2 h>
T2SL2 0 0 0 0 1 1 1 1 T2CN 0 1 T2ST 0 1
T2SL1 0 0 1 1 0 0 1 1
T2SL0 0 1 0 1 0 1 0 1
Input clock selection PS5 PS6 PS7 PS8 PS9 ( 8us)
( 16us) ( 32us) ( 64us) ( 128us)
PS10 ( 256us) PS11 ( 512us) PS12 (1024us)
Timer2 Counter Continuation/Pause Control Count pause Count contination Timer2 Start/Stop Control Timer2 Stop Timer2 Start after clear
Figure 11-11 Timer2 Mode Register
7 IEDS -
2) External Interrupt Signal Edge Selection Register
IED2H IED2L IED1H IED1L -
0 W <00CB h>
IED*H 0 0 1 1
IED*L 0 1 0 1
INT* Falling Edge Selection Rising Edge Selection Both Edge Selection
Figure 11-12 External Interrupt Signal Edge Selection Register
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(3) Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register (TDR), the up-counter is cleared to 00 h, and interrupt (IFT0, IFT1) is occured at the next clock.
T0 Data Registers Value T0 Value
Concurrence
Concurrence
Concurrence
0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT
IFT0 Interval period
Figure 11-13 Operatiion of Timer0
For Timer0, the internal clock (PS) and the external clock (EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock. As internal clock. Timer0 can be used as internal-timer which period is determined by Timer Data Register (TDR). Chosen as external clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are used to stop and start Timer0 and Timer1 without clearing the counter. T0ST, T1ST is used to clear the counter. For clearing and starting the counter, T0ST or T1ST should be temporarily set to 0 and then set to 1. T0CN, T1CN, T0ST and T1ST should be set 1, when Timer counting-up. Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0 to 1, the period of signal from INT2 can be measured and then, event counter value for INT2 can be read. During counting-up, value of counter can be read. Timer execution is stopped by the reset signal (RESET
= L)
Note: In the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. If not, caution should be taken in the selection of upper 8-bit data.
(Example) 1) Upper 8-bit Read 0A 0A 2) Lower 8-bit Read FF 01 3) Upper 8-bit Read 0B 0B ===================== -
0AFF 0B01
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T0 Data Register Value T0 Value
Concurrence
Concurrence
0
CLEAR INTERRUPT
CLEAR INTERRUPT
IFT0 0 1 Clear & Start
T0ST
T0CN
0
1
Counter Stop Count Clear & Count Stop Count Clear & Start continue
Figure 11-14 Start/Stop operation of Timer0
T3
T2
T1 T0
INT2
Figure 11-15 Input capture operation of Timer0
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* Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM01) output level of Timer Output port. If initial level is L, Low-Data Register value of Timer Data Register is transferred to comparator and T0OUT (T1OUT) is to be Low, if initial level is High? High -Data Register is transferred and to be High. Single Mode can be set by Mode Select bit (T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to 1 When used as Single Mode, Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD (T1MOD) should be set 0. Counter counts up until the value of Data Register and occurs Time-out interrupt. The level of Timer Output port toggle and repeats process of counting the value which is selected in Data Register. During Modulo-N Mode, If interrupt select bit (T0IFS, T1IFS) of Mode Register is 0, Interrupt occurs on every Time-out. If it is 1, Interrupt occurs every second time-out.
(*note. Timer Output is toggled whenever time Note: out happen)
[ Single Mode ]
8bit / 16bit counting
Timer Enable initial. value toggle.
Timer-output toggle. interrupt occurs. count stop.
[ Modulo-N Mode ]
8bit / 16bit counting
Timer Enable initial. value toggle. Timer-Output Toggle. Int occurs (IFS = 1) Each 2nd time out. Int occurs (IFS = 0) When Time out.
Figure 11-16 Operation Diagram for Single/Modulo-N Mode
(4) Timer 2 Timer2 operates as a up-counter. The content of T2DR are compared with the contents of up-counter. If a match is found. Timer2 interrupt (IFT2) is generated and the upcounter is cleared to 00 h. Therefore, Timer2 executes as a interval timer. Interrupt period is determined by the count source clock for the Timer2 and content of T2DR. When T2ST is set to 1, count value of Timer 2 is cleared and starts counting-up. For clearing and starting the Timer2. T2ST have to set to 1 after set to 0. In order to write a value directly into the T2DR, T2ST should be set to 0. Count value of Timer2 can be read at any time.
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T2 Data Registers Value T2 Value
Concurrence
Concurrence
Concurrence
0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT
IFT0 Interval period
Figure 11-17 Operation of Timer2
T2 Data Register Value T2 Value
Concurrence
Concurrence
0
CLEAR INTERRUPT
CLEAR INTERRUPT
IFT2 count stop by 0 count start clear by 1
T2ST
Counter Count up Count Stop Count continue Count up after clear
Figure 11-18 Start/Stop of Timer2
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12. INTERRUPTS
The GMS81C50 Series interrupt circuits consist of Interrupt Mode Register (MOD), Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Priority circuit and Master enable flag ("I" flag of PSW). 8 interrupt sources are provided. The configuration of interrupt circuit is shown in Figure 12-1 . The GMS81C50 Series contains 8 interrupt sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is nonmaskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key Scan) - 8 interrupt vector - Nested interrupt control is possible - Programmable interrupt mode - Hardware accept mode - Software selection accept mode - Read and write of interrupt request flag are possible. - In interrupt accept, request flag is automatically cleared.
Internal Data Bus
0 -
IENL -
7 -
0 -
IENH -
7
0
IMOD -
7 -
KSCN INT1 INT2 IFT0 IFT1 IFT2 IFWDT IFBIT
KSCNR INT1R INT2R T0R T1R T2R WDTR BRK BITR IRQ Standby Mode Release PRIORITY CONTROL INT. VECTOR ADDR.
Figure 12-1 Block Diagram of Interrupt
12.1 Interrupt priority and sources.
Each interrupt vector is independent and has its own priority. Software interrupt (BRK) is also available. Interrupt source classification is shown in Table 12-1.
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Mask non-maskable
Priority 0 1 2
Interrupt Source RST (RESET pin) KSCNR (Key Scan) INT1R (External Interrupt1) INT2R (External Interrupt2) T0R (Timer0) T1R (Timer1) T2R (Timer2) WDTR (Watctdog Timer) BITR (Basic Interval Timer) BRK instruction
INT Vector High FFFF FFFB FFF9 FFF7 FFF3 FFF1 FFEF FFE9 FFE7 FFDF
INT Vector Low FFFE FFFA FFF8 FFF6 FFF2 FFF0 FFEE FFE8 FFE6 FFDE
Hardwar e Interrupt
maskable
3 4 5 6 7
-
-
Table 12-1 Interrupt Priority & Source
12.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag = 0, all interrupts become disable. When I flag = 1, interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The accepted interrupt request flag is automatically cleared during interrupt cycle process. The interrupt request flag maintains 1 until the interrupt is accepted or is cleared in program. In reset state, interrupt request flag register (IRQH, IRQL) is cleared to 0. It is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (Refer to software interrupt).
IEN L
IENH IRQL IRQH
R/W <00CCh>
KSCNE KSCNE WDTR INT1E WDTR INT1R BITE INT2E BITE INT2R T0E T0R T1E T1R T2E T2R -
R/W <00CEh> R/W <00CDh> R/W <00CFh>
IENL : INTERRUPT ENABLE REGISTER LOW IENH : INTERRUPT ENABLE REGISTER HIGH IRQL : INTERRUPT REQUEST REGISTER LOW IRQH : INTERRUPT REQUEST REGISTER HIGH
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12.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit (IM1, IM0) of IMOD register.
7 IMOD -
Interrupt Mode Register
IM1 IM0 IP3 IP2 IP1
0 IP0 R/W <00CA h>
Assigning by interrupt accept mode bit IM1 0 0 1 IM0 0 1 * fixed by hardware changeable by IP3~ IP0 Interrupt is inhibited Priority
(1) Selection of Interrupt by IP3-IP0 The condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be 1. In Reset state, these IP3 - IP0 registers become all 0.
IP3 0 0 0 0 0 0 0 1 1 1 1 1
IP2 0 0 0 1 1 1 1 0 0 0 0 1
IP1 0 1 1 0 0 1 1 0 0 1 1 0
IP0 1 0 1 0 1 0 1 0 1 0 1 0
Selection Interrupt KSCNR (Key Scan) INT1R (External interrupt 1) INT2R (External interrupt 2) Reserved T0R (Timer 0) T1R (Timer 1) T2R (Timer 2) Reserved Reserved WDTR (Watch Dog Timer) BITR (Basic Interval Timer) Reserved
Table 12-2 Interrupt Selection by IP3 - IP0
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(2) Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Figure 12-2 Interrupt Enable Accept Timing
*Interrupt Request sampling time -Maximum 12 machine cycle (When execute DIV instruction) -Minimum 0 machine cycle
*Interrupt preprocess step is 8 machine cycle *Interrupt overhead -Maximum 1 + 12 + 8 = 21 machine cycle -Minimum 1 + 0 + 8 = 9 machine cycle
(3) The valid timing after executing Interrupt control instructions I flag is valid just after executing of EI/DI on the contrary. Interrupt Enable register is valid one instruction after controlling interrupt Enable Register.
12.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. After the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occured.As soon as an interrupt is accepted, the content of the program counter and PSW are savedin the stack area. At the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. In order to execute the interrupt service routine, it is necessary to write the jump addresses in the vector table (FFE0 h ~ FFFF h) corresponding to each interrupt
* Interrupt Processing Step 1) Store upper byte of Program Counter, SP <= SP 2) Store lower byte of Program Counter, SP <= SP - 1 3) Store Program Status Word, SP <= SP - 2 4) After resetting of I-flag, clear accepted Interrupt Request Flag. (Set B-flag for BRK Instruction) 5) Call Interrupt service routine
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clock
Interrupt Process Step ISR *1
SYNC
R/W internal addr bus internal data bus internal READ internal WRITE
*2 PC SP SP-1 SP-2 LVA *3 HVA new PC
OP CODE
=
OP CODE
=
PCH
=
PCL
=
PSW
=
L vector
=
H vector
=
*1 ISR *2 LVA *3 HVA
: Interrupt Service Routine : Low Vector Address : High Vector Address
Figure 12-3 Interrupt Procesing Step Timing
12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
S o f t w ar e in t e r r u p t i s a v ai l ab l e j u s t b y w r i t in g Break(BRK) instruction. The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set and I flag is reset.
Flag change by BRK execution
PSW N V G B H I Z C
set PSW N V G 1 H 0
reset Z C
(Right after BRK execution)
Interrupt vector of BRK instruction is shared by vector of Table Call (TCALL0). When both instruction of BRK and TCALL0 are used, as shown in Figure 12-4 each process-
ing routine is judged by contents of B flag. There is no instruction to reset directly B flag.
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B flag 1 BRK or TCALL0 BRK INTERRUPT ROUTINE
0
TCALL0 ROUTINE
RETI
RET
Figure 12-4 Execution of BRK or TCALL0
12.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before entering the Interrupt Service Routine. After then, no interrupt is accepted. If EI instruction is executed, interrupt mask enable bit becomes 1, and each enable bit can accept interrupt request. When two or more interrupts are generated simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
12.7 Key Scan Input Processing
(1) Standby Mode Release Register (SMRR) Key Scan Interrupt is generated by detecting low or high Input from each Input pin (R0, R1) is one of the sources which release standby (SLEEP, STOP) mode. Key Scan ports are all 16bit which are controlled by Standby Mode Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be set for correct interrupt executing, SLEEP mode and STOP mode, the rest of executing is the same as that of external Interrupt. Each SMRR Register bit is allowed for each port (for Bit= 0, no Key Input, for Bit= 1, Key Input available). At reset, SMRR becomes 00 h. So, there is no Key Input source.
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7
0 W <00DC h>
SMRR0
R00 R01 . . . R07
Internal Key Scan Interrupt R0 port Selection Logic
7
0 W <00DD h>
SMRR1
R10 R11 . . . R17
R0 port Selection Logic
Figure 12-5 Key Scan Block
7 SMRR0 KR07 KR06 KR05
SMRR0 Register
KR04 KR03 KR02 KR01
0 KR00 W <00DC h>
7 SMRR1 KR17 KR16 KR15
SMRR1 Register
KR14 KR13 KR12 KR11
0 KR10 W <00DD h>
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SMRR0 0 KR07 1 0 KR06 1 0 KR05 1 0 KR04 1 0 KR03 1 0 KR02 1 0 KR01 1 0 KR00 1
SMRR1 0 KR17 1 0 KR16 1 0 KR15 1 0 KR14 1 0 KR13 1 0 KR12 1 0 KR11 1 0 KR10 1
Key Input Selection no select select no select select no select select no select select no select select no select select no select select no select select
(2) Standby Release Level Control Register (SRLC) Standby release level control register (SRLC) can select the key scan input level L or H for standby release by each bit pin (R0, R1). Standby release level control register (SRLC) is write-only register and initialized as 00 h in reset state.
7 SRLC0 KLR07 KLR06 KLR05
SRLC0 Register
KLR04 KLR03 KLR02 KLR01
0 KLR00 W <00F6 h>
7 SRLC1 KLR17 KLR16 KLR15
SRLC1 Register
KLR14 KLR13 KLR12 KLR11
0 KLR10 W <00F7 h>
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SRLC0 0 KLR07 1 0 KLR06 1 0 KLR05 1 0 KLR04 1 0 KLR03 1 0 KLR02 1 0 KLR01 1 0 KLR00 1
SRLC1 0 KLR17 1 0 KLR16 1 0 KLR15 1 0 KLR14 1 0 KLR13 1 0 KLR12 1 0 KLR11 1 0 KLR10 1
Key Input Level Low High Low High Low High Low High Low High Low High Low High Low High
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13. WATCH DOG TIMER
Watch Dog Timer (WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch Dog Timer Register (WDTR).
0 IFBIT WDT0 WDT1 WDT2 WDT3 WDT4
5 CLR WDT5 To Reset circuit WDTON
6BIT COMPARATOR
IF WDT
WDTR
WDTR0 0
WDTR1
WDTR2
WDTR3
WDTR4
WDTR5
WDTCL 6
W <00C8 h>
Internal Data Bus
Figure 13-1 Block diagram of Watch Dog Timer
13.1 Control of WDT
Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting bit5 (WDTON) of Clock Control Register (CKCTLR).
7 CKCTLR
Clock Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7 h>
-
WDTON 0 1
Watch Dog Timer Function Control 6-bit Timer Watch Dog Timer
By assigning bit6(WDTCL) of WDTR, 6-bit counter can
be cleared.
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7 WDTR
Watch DOG Timer Register
WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1
0 WDTR0 W <00C8 h>
-
Determine Interval of IFWDT Interval of IFWDT = Value of WDTR > Interval of IFBIT WDTCL 0 1 Watch Dog Timer Operation free-run Automatically cleared, after one machine cycle
13.2 WDT Interrupt Interval
WDT Interrupt (IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register. -Interval of IFWDT = (IFBIT interval) * (WDTR value) -Interval of IFWDT : 512 us * 1 = 512 us (MIN>) -65,536us * 63 = 4,128,768 us (MAX>) As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input clock cycle is possible from 512 us to 65,536 us by BTS. (at fex = 4MHz)
*At Hardware reset time ,WDT starts automatically. Therefore, the user must select the CKCTLR, WDTR before WDT overflow. -Reset WDTR value = 0F h,15 -interval of WDT = 65,536 * 15 = 983040 us (about 1second )
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7 CKCTLR
Clock Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7 h>
-
BTS2 0 0 0 0 1 1 1 1
BTS1 0 0 1 1 0 0 1 1
BTS0 0 1 0 1 0 1 0 1
WDT Input clock 512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us
Max. Interval of WDT Output (*note1) 32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us
Device come into the reset state by WDT N o t e : W h en W D T R R eg i st e r v al u e is 6 3 ( 3F h ) (Caution) : Do not use 0 for WDTR Register value.
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14. STANDBY FUNCTION
To save power consumption, there is STOP modes. In this modes, the execution of program stops.
14.1 Sleep Mode
SLEEP mode can be entered by setting the bit of SLEEP mode register (SLPM). In the mode, CPU clock stops but oscillator keeps running. B.I.T and a part of peripheral hardware execute, but prescaleris output which provide clock to peripherals can be stopped by program. (Except, PS10 canit stopped.) In SLEEP mode, more consuming power can be saved by not using other peripheral hardware except for B.I.T. By setting ENPCK (peripheral clock control bit) of CKCTLR (clock control register) to 0, peripheral hardware halted, and SLEEP mode is entered. To release SLEEP mode by BITR (basic interval timer interrupt), bit10 of prescaler should be selected as B.I.T input clock before entering SLEEP mode. NOP instruction should be follows setting of SLEEP mode for rising precharge time of data bus line. (ex) setting of SLEEP mode : set the bit of SLEEP ; mode register (SLPM) NOP : NOP instruction
7 SLPM
SLEEP MODE CONTROL Register
-
0 SLPM0 W <00F0 h>
-
-
-
-
-
SLPM0 0 1
condition sleep mode release sleep mode
7 CKCTLR
Colck Control Register
WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C8 h>
-
ENCPK 0 1
Peripheral Clock stopped provided
14.2 STOP MODE
STOP mode can be entered by STOP instruction during program. In STOP mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. All registers and RAM data are preserved. NOP instruction should be follows STOP instruction for rising precharge time of Data Bus line. (ex) STOP NOP : STOP instruction execution : NOP instruction
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OSC. Circuit
Clock Pulse GEN CLR
CPU Clock
MUX Basic Interval Timer CLR Prescaler CLR B.I.T 7
STOP
S R
Q
S R
Q
Control Signal
Overflow Detection
Release Signal From Interrupt Circuit RESET
Figure 14-1 Block Diagram of Standby Circuit
Prescaler
ENPCK
PS10
Selector
Basic Interval Timer
Peripheral
Figure 14-2 ENPCK and Basic Interval Timer Clock
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14.3 STANDBY MODE RELEASE
Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2 ~ BTS0 and set ENPCK to 1.
Release Signal RESET KSCN (key input) INT1 , INT2 B.I.T
SLEEP O O O O
STOP O O O X
Table 14-1 Standby Mode Register
Release Factor RESET
Release Method By RESET Pin = Low level, Standby mode is release and system is initialized Standby mode is released by low input of selected pin by key scan Input (SMRR0, SMRR1) In case of interrupt mask enable flag = 0, program executes just after standby instruction, if flag = 1, enters each interrupt service routine. When external interrupt (INT1, INT2) enable flag is 1, standby mode is released at the rising edge of each terminal. When Standby mode is released at interrupt. Mask Enable flag = 0, program executes from the next instruction of standby instruction. When 1, enters each interrupt service routine. When B.I.T is executed only by bit10 of prescaler (PS10), SLEEP mode can be release. Interrupt release SLEEP mode, when BIT interrupt enable flag is 1. When standby mode is released at interrupt. Mask enable flag = 0, program executes from the next instruction of SLEEP instruction. When 1, enters each interrupt service routine.
KSCN (key input)
INT1 INT2
Basic Interval Timer (IFBIT)
Table 14-2 Standby Mode Release
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[ SLEEP MODE ]
Xin
SLEEP command
SLEEP Mode
release by interrupt
RESET
Longer than 2 machine cycle
[ STOP MODE ]
clock
STOP Mode Stable OSC. time
release by interrupt
Program Setting Time by CKCTLR
RESET
Longer than stable OSC. Time
Figure 14-3 Release Timing of Standby Mode
14.4 RELEASE OPERATION OF STANDBY MODE
After standby mode is released, the operation begins according to content of related interrupt register just before standby mode start (Figure 14-4 ) (1) Interrupt Enable Flag(I) of PSW = 0 Release by only interrupt which interrupt enable flag = 1, and starts to execute from next to standby instruction (SLEEP or STOP). (2) Interrupt Enable Flag(I) of PSW = 1 Released by only interrupt which each interrupt enable flag = 1, and jump to the relevant interrupt service routine.
Note: When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10 (PS10) of prescaler is selected or peripheral hardware clock control bit (ENPCK) to 1, Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, standby mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both 1, standby mode is not entered.
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STOP Command
Standby Mode
Interrupt Request GEN.
0 IE Flag 1 Standby Mode Release
PSW IE Flag 1 Interrupt Service Routine
0
Standby Next Command Execution
Figure 14-4 Standby Mode Release Flow
Internal circuit Oscillator Internal CPU clock Register RAM I/O port Prescaler Basic Interval Timer Watch Dog Timer Timer Address Bus, Data Bus
SLEEP mode Active Stop Retained Retained Retained Active PS10 selected : Active Others : Stop Stop Stop Retained Stop Stop
STOP mode
Retained Retained Retained Retained Stop Stop Stop Retained
Table 14-3 Operation State in Standby Mode
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15. OSCILLATION CIRCUIT
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator. As shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin. Clock from oscillation circuit makes CPU clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. Alternately, the oscillator may be driven from an external source as shown is Fig. 4.2.-(b). In the Standby (STOP) mode, oscillatiion stop, Xout state goes to HIigh, Xin state goes to Low, and built-in feed back resistor is disabled.
(a) External Crystal (Ceramic) oscillator circuit
Cout Xout
Xin Cin
(b) External clock input circuit
Xout
Xin
External clock
Figure 15-1 Oscillator configurations
* Recommendable resonator
Frequency
Resonator Maker
CQ
Part Name
ZTA4.00MG FCR4.0MC5 FCR4.0M5 CCR4.0MC3
Load Capacitor
Cin=Cout=30pF Cin=Cout=open Cin=Cout=33pF
Operating Voltage
2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V
4.0 MHz
TDK TDK TDK
* MC type is building in load capacitior.CCR type is chip type.
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16. RESET FUNCTION
16.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for stable system initialization. The RESET pin contains a Schmitt trigger with an internal pull-up resistor.
RESET
0.1 uF Capacitor
Figure 16-1
16.2 POWER ON RESET
Power On Reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, RESET terminal is maintained at L Level until a crystal ceramic oscillator oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4MHz).The execution of built-in Power On Reset circuit is as follows : (1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow detection circuit. (2) Once B.I.T Overflow detection circuit is reset. Then, Prescaler starts to count. (3) Prescaler output is inputted into B.I.T and PS10 of Prescaler output is automatically selected. If overflow of B.I.T is detected, Overflow detection circuit is set. (4) Reset circuit generates maximum period of reset pulse from Prescaler and B.I.T.
Internal IC
VDD
RESET 0.1uF
Internal Reset
Power On DET Pulse GEN.
VSS
XTAL OSC.
CLR Prescaler
PS10
CLR Basic Interval Tiemr
MSB
CLR Basic Interval Tiemr
Figure 16-2 Block Diagram of Power On Reset Circuit
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Note: Notice ; When Power On Reset, oscillator stabilization time doesnt include OSC. Start time.
??
$ 14$ 26%%1 %
2 %1 %%,8,6@
Figure 16-3 Oscillator stabilization diagram
RESET
INTERNAL RESET ADDR. BUS
SP
SP-1
SP-2
FFFE FFFF
NEW PC
INTERNAL DATA BUS
FE
LSB MSB VECTOR VECTOR
Figure 16-4 Reset Timing by Diagram
16.3 Low Voltage Detection Mode
(1) Low voltage detection condition An on board voltage comparator checks that VDD is at the required level to ensure correct operation of the device. If VDD is below a certain level, Low voltage detector forces the device into low voltage detection mode. (2) Low Voltage Detection Mode There is no power consumption except stop current, stop mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode, all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet ,the default pull up option (all port connect to pull-up resis-
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tor ) is selected. (3) Release of Low Voltage Detection Mode Reset signal result from new battery(normally 3V) wakes
the low voltage detection mode and come into normal reset state. It depends on user whether to execute RAM clear routine or not.
4*'(
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 10 20 30 40 50 60 70
%'(
Figure 16-5 Low Voltage vs Temperature
(4) SRAM BACK-UP after Low Voltage Detection.
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3.0V about hours depend on Vcc-Gnd Capacitor
MCU OPR. Voltage Low Voltage Detection point
1.8V(TYP) ( 20(
Power On Reset ( SRAM retention)
0.7V(VRET) 0V * SRAM Data Backup * The operation after Low voltage detection Interrupt : disable User Stop release : disable Removes All I/O port : input Mode Batteries Remout port : Low Level OSC : STOP All I/O port pull-up ON (Mask Option ) SRAM Data retention
Power On Reset ( SRAM unstable )
User Replace Batteries
Figure 16-6 Low Voltage Detection and Protection
(5) S/W flow chart example after Reset using SRAM Back-up
RESET Stack Pointer initialize
Check the SRAM value (RAM Pattern, Check sum..)
SRAM DATA IS VALID? Y Use saved SRAM value
N
Clear All Ram area
Figure 16-7 S/W Flow Chart Example for SRAM Back-up
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16.4 Low Voltage Indicator Register (LVIR)
Low Voltage Indication Register (LVIR) is read only Register. It is useful to display the consumption of Batteries. If VDD power level is below a cirtain level which is higher than low voltage detection level ( refer to Figure 16-6 ) , The bit of LVIR register could be set according to the VDD level sequentially. The VDD dection levels for Indication are two , that is , Bit1 and Bit0 of LVIR Register. The detection level of Bit0 is higer than Bit1.
bit LVIR initial value R/W
7 -
6 -
5 -
4 -
3 -
2 -
1 LVIR1 0 R
0 LVIR0 0 R <00EF h>
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80
Appendix A. GMS800 Series Instruction
1. Instruction Map
LOW HIGH 000 00000 00 00001 01 SET1 dp.bit 00010 02 BBS A.bit,rel 00011 03 BBS dp.bit,rel 00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm 00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp 00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X 00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs 01000 08 ASL A ROL A LSR A ROR A INC A DEC A 01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp 01010 0A TCALL 0 TCALL 2 TCALL 4 TCALL 6 TCALL 8 TCALL 10 TCALL 12 TCALL 14 01011 0B SETA1 .bit CLRA1 .bit NOT1 M.bit OR1 OR1B AND1 AND1B EOR1 EOR1B LDC LDCB STC M.bit 01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp 01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y 01110 0E PUSH A PUSH X PUSH Y PUSH PSW 01111 0F
BRK
001
CLRC
//
//
//
BRA rel PCALL Upage
010
CLRG
//
//
//
011
DI
//
//
//
RET
100
CLRV
//
//
//
TXSP
INC X DEC X
101
SETC
//
//
//
TSPX
110
SETG
//
//
//
TXA
XCN
DAS
111
EI
//
//
//
TAX
XAS
STOP
LOW HIGH 000
10000 10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1 dp.bit
10010 12 BBC A.bit,rel
10011 13 BBC dp.bit,rel
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs
11100 1C BIT !abs TEST !abs TCLR1 !abs CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs
11101 1D ADDW dp SUBW dp CMPW dp LDYA dp INCW dp DECW dp STYA dp CBNE dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y
11111 1F JMP [!abs] JMP [dp] CALL [dp]
001
//
//
//
010
//
//
//
MUL
011
//
//
//
DBNE Y
RETI
100
//
//
//
DIV
TAY
101
//
//
//
XMA {X} LDA {X}+ STA {X}+
TYA
110
//
//
//
XAY
DAA
111
//
//
//
XYX
NOP
A-1
Appendix A. GMS800 Series Instruction
2. Alphabetic order table of instruction
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} ADDW dp AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} AND1 M.bit AND1B M.bit ASL A ASL dp ASL dp + X ASL !abs BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BIT dp BIT !abs BMI rel BNE rel BPL rel BRA rel BRK OP CODE 04 05 06 07 15 16 17 14 1D 84 85 86 87 95 96 97 94 8B 8B 08 09 19 18 y2 y3 x2 x3 50 D0 F0 0C 1C 90 70 10 2F 0F BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 2 3 3 2 2 1 3 3 1 2 2 3 2 3 2 3 2 2 2 2 3 2 2 2 2 1 CYCLE NO 2 3 4 4 5 6 6 3 5 2 3 4 4 5 6 6 3 4 4 2 4 5 5 4/6 5/7 4/6 5/7 2/4 2/4 2/4 4 5 2/4 2/4 2/4 4 8 Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Arithmetic shift left -------C -------C N-----Z16-bits add without carry : YA YA + (dp+1)(dp) Logical AND A A ^ (M) NV - - H - ZC NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Bit test A with memory : Z A ^ M, N (M7), V (M6) Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PCL), SP S - 1, M(SP) PSW, SP SP - 1, PCL (0FFDEH), PCH (0FFDFH)
--------------MM - - - - Z --------------MM - - - - Z -----------------------------
---1-0--
38 39
BVC rel BVS rel
30 B0
2 2
2/4 2/4
Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel
---------------
A-2
Appendix A. GMS800 Series Instruction
NO. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
MNENONIC CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel CLR1 dp.bit CLR1A A.bit CLRC CLRG CLRV CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPW dp CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DBNE dp,rel DBNE Y,rel DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DECW dp DI DIV EI
OP CODE 3B 5F FD 8D y1 2B 20 40 80 44 45 46 47 55 56 57 54 5D 5E 6C 7C 7E 8C 9C 2C DF CF AC 7B A8 A9 B9 B8 AF BE BD 60 9B E0
BYTE NO. 3 2 3 3 2 2 1 1 1 2 2 2 3 3 2 2 1 2 2 2 3 2 2 3 2 1 1 3 2 1 2 2 3 1 1 2 1 1 1
CYCLE NO 8 8 5/7 6/8 4 2 2 2 2 2 3 4 4 5 6 6 3 4 2 3 4 2 3 4 4 3 3 5/7 4/6 2 4 5 5 2 2 6 3 12 3 Subroutine call
OPERATION
FLAG NVGBHIZC --------
M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Compare accumulator contents with memory contents A - (M)
----------------------------0 --0-----0--0---
N - - - - - ZC
Compare YA contents with memory pair contents : YA - (dp+1)(dp) Compare X contents with memory contents X - (M) Compare Y contents with memory contents Y - (M) 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement and branch if not equal : if (M) 0, then PC PC + rel. Decrement MM-1
N - - - - - ZC
N - - - - - ZC
N - - - - - ZC N-----ZN - - - - - ZC N - - - - - ZC --------
N-----Z-
Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Disable interrupts : I "0" Divide : YA/X Q:A, R:Y Enable interrupts : I "1"
N-----Z-----0-NV - - H - Z -----1--
A-3
Appendix A. GMS800 Series Instruction
NO. 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123
MNENONIC EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} EOR1 M.bit EOR1B M.bit INC A INC dp INC dp + X INC !abs INC X INC Y INCW dp JMP !abs JMP [!abs] JMP [dp] LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDC M.bit LDCB M.bit LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs LDYA dp LSR A LSR dp LSR dp + X LSR !abs
OP CODE A4 A5 A6 A7 B5 96 97 94 AB AB 88 89 99 98 8F 9E 9D 1B 1F 3F C4 C5 C6 C7 D5 D6 D7 D4 DB CB CB E4 1E CC CD DC 3E C9 D9 D8 7D 48 49 59 58
BYTE NO. 2 2 2 3 3 2 2 1 3 3 1 2 2 3 1 1 2 3 3 2 2 2 2 3 3 2 2 1 1 3 3 3 2 2 2 3 2 2 2 3 2 1 2 2 3
CYCLE NO 2 3 4 4 5 6 6 3 5 5 2 4 5 5 2 2 6 3 5 4 2 3 4 4 5 6 6 3 4 4 4 5 2 3 4 4 2 3 4 4 5 2 4 5 5 Load X-register Y (M) Load accumulator A (M) Exclusive OR A A (M)
OPERATION
FLAG NVGBHIZC
N-----Z-
Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Increment (M) (M) + 1
-------C -------C N - - - - - ZC
N-----Z-
Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 Unconditional jump PC jump address
N-----Z--------
N-----Z-
X-register auto-increment : A (M), X X + 1 Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------C -------C --------
N-----Z-
Load YA : YA (dp+1)(dp) Logical shift right
N-----Z-
76543210 C "0"
N - - - - - ZC
A-4
Appendix A. GMS800 Series Instruction
NO. 124 125 126 127 128 129 130 131 132 133 134 135 136 137
MNENONIC MUL NOP NOT1 M.bit OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} OR1 M.bit OR1B M.bit PCALL
OP CODE 5B FF 4B 64 65 66 67 75 76 77 74 6B 6B 4F
BYTE NO. 1 1 3 2 2 2 3 3 2 2 1 3 3 2
CYCLE NO 9 2 5 2 3 4 4 5 6 6 3 5 5 6 No operation
OPERATION Multiply : YA Y x A Bit complement : (M.bit) ~(M.bit) Logical OR A A V (M)
FLAG NVGBHIZC N-----Z---------------
N-----Z-
Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PCL (upage), PCH "OFFH"
-------C -------C --------
138 139 140 141 142 143 144 145 146 147
POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI
0D 2D 4D 6D 0E 2E 4E 6E 6F 7F
1 1 1 1 1 1 1 1 1 1
4 4 4 4 4 4 4 4 5 6
Pop from stack SP SP + 1, Reg. M(SP) -------(restored) Push to stack M(SP) Reg. SP SP - 1 --------
Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP)
--------
(restored)
148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163
ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X}
28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34
1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1
2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3
Rotate left through carry
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
A-5
Appendix A. GMS800 Series Instruction
NO. 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188
MNENONIC SET1 dp.bit SETA1 A.bit SETC SETG STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STC M.bit STOP STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs STYA dp SUBW dp TAX TAY TCALL n
OP CODE x1 0B A0 C0 E5 E6 E7 F5 F6 F7 F4 FB EB 00 EC ED FC E9 F9 F8 DD 3D E8 9F nA
BYTE NO. 2 2 1 1 2 2 3 3 2 2 1 1 3 1 2 2 3 2 2 3 2 2 1 1 1
CYCLE NO 4 2 2 2 3 4 4 5 6 6 3 4 6 3 4 5 5 4 5 5 5 5 2 2 8
OPERATION Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store accumulator contents in memory (M) A
FLAG NVGBHIZC ---------------------1 --1-----
--------
X-register auto-increment : (M) A, X X + 1 Store C-flag : (M.bit) C Stop mode (halt CPU, stop oscillator) Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp) Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PCL (Table vector L), PCH (Table vector H) ---------------------NV - - H - ZC N-----ZN-----Z----------------------
189 190 191 192 193 194 195 196 197 198 199 200 201 202
TCLR1 !abs TSET1 !abs TSPX TST dp TXA TXSP TYA XAX XAY XCN XMA dp XMA dp + X XMA {X} XYX
5C 3C AE 4C C8 8E BF EE DE CE BC AD BB FE
3 3 1 2 1 1 1 1 1 1 2 2 1 1
6 6 2 3 2 2 2 4 4 5 5 6 5 4
Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) Transfer stack-pointer contents to X-register : X SP Test memory contents for negative or zero : (dp) - 00H Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA Exchange nibbles within the accumulator: A7 ~ A4 f A3 ~ A0 Exchange memory contents with accumulator (M) f A Exchange X-register contents with Y-register : X f Y
N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------N-----Z-
N-----Z--------
A-6
Appendix A. GMS800 Series Instruction
2.1 Instruction Table by Function 1. Arithmetic/Logic Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNENONIC ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs+Y ADC [dp+X] ADC [dp]+Y ADC {X} AND #imm AND dp AND dp + X AND !abs AND !abs+Y AND [dp+X] AND [dp] + Y AND {X} ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [dp + X] CMP [dp] + Y CMP {X} CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y DIV OP CODE 04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE 9B BYTE NO. 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1 1 CYCLE NO 2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 12 Divide : YA/A Q:A, R:Y NV - - H - Z 1's complement : (dp) ~(dp) Decimal adjust for addition Decimal adjust for substraction Decrement MM-1 N-----ZN-----ZN - - - - - ZC N - - - - - ZC Compare Y contents with memory contents Y - (M) N - - - - - ZC Compare X contents with memory contents X - (M) N - - - - - ZC N - - - - - ZC Arithmetic shift left N-----ZLogical AND A A ^ (M) NV - - H - ZC Add with carry. A A + (M) + C OPERATION FLAG NVGBHIZC
C
76543210 "0"
N - - - - - ZC
Compare accumulator contents with memory contents A - (M)
A-7
Appendix A. GMS800 Series Instruction
NO. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
MNENONIC EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X] EOR [dp] + Y EOR {X} INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [dp +X} OR [dp] + Y OR {X} ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [dp + X] SBC [dp] + Y SBC {X} TST dp XCN
OP CODE A4 A5 A6 A7 B5 96 97 94 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
BYTE NO. 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
CYCLE NO 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Logical shift right Increment (M) (M) + 1 Exclusive OR A A (M)
OPERATION
FLAG NVGBHIZC
N-----Z-
N - - - - - ZC
N-----Z-
76543210 C "0"
Multiply : YA Y x A Logical OR A A V (M)
N - - - - - ZC
N-----Z-
N-----Z-
Rotate left through carry
C
76543210
N - - - - - ZC
Rotate right through carry
76543210 C
Substract with carry A A - (M) - ~(C)
N - - - - - ZC
NV - - HZC
Test memory contents for negative or zero : (dp) - 00H Exchange nibbles within the accumulator: A7 ~ A4 f A3 ~ A0
N-----ZN-----Z-
A-8
Appendix A. GMS800 Series Instruction
2. Register / Memory Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 MNENONIC LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [dp + X] LDA [dp]+Y LDA {X} LDA {X}+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + Y LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [dp + X] STA [dp] + Y STA {X} STA {X}+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp + X XMA {X} XYX OP CODE C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE BYTE NO. 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1 CYCLE NO 2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 3 4 4 5 6 6 3 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Exchange X-register contents with Y-register : X f Y -------Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X SP Transfer X-register contents to accumulator : A X Transfer X-register contents to stack-pointer : SP X Transfer Y-register contents to accumulator : A Y Exchange X-register contents with accumulator : X fA Exchange Y-register contents with accumulator : Y fA Exchange memory contents with accumulator (M) f A N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----Z--------------Store Y-register contents in memory (M) Y -------X-register auto-increment : (M) A, X X + 1 Store X-register contents in memory (M) X --------------Store accumulator contents in memory (M) A Load X-register Y (M) N-----ZX-register auto-increment : A (M), X X + 1 Load memory with immediate data : (M) imm Load X-register X (M) N-----Z-------N-----ZLoad accumulator A (M) OPERATION FLAG NVGBHIZC
A-9
Appendix A. GMS800 Series Instruction
3. 16-Bit Operation
NO. 1 2 3 4 5 6 7 MNENONIC ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp OP CODE 1D 5D BD 9D 7D DD 3D BYTE NO. 2 2 2 2 2 2 2 CYCLE NO 5 4 6 6 5 5 5 OPERATION 16-bits add without carry : YA YA + (dp+1)(dp) Compare YA contents with memory pair contents : YA - (dp+1)(dp) Decrement memory pair : (dp+1)(dp) {(dp+1)(dp)} - 1 Increment memory pair : (dp+1)(dp) {(dp+1)(dp)} + 1 Load YA : YA (dp+1)(dp) Store YA : (dp+1)(dp) YA 16-bits substract without carry : YA YA - (dp+1)(dp) N-----ZN-----ZN-----Z-------NV - - H - ZC FLAG NVGBHIZC NV - - H - ZC N - - - - - ZC
4. Bit Manipulation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNENONIC AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLR1A A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs OP CODE 8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C BYTE NO. 3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3 CYCLE NO 4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6 OPERATION Bit AND C-flag : C C ^ (M.bit) Bit AND C-flag and NOT : C C ^ ~(M.bit) Bit test A with memory : Z A ^ M, N (M7), V (M6) Clear bit : (M.bit) "0" Clear A.bit : (A.bit) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C C (M.bit) Bit exclusive-OR C-flag and NOT : C C (M.bit) Load C-flag : C (M.bit) Load C-flag with NOT : C ~(M.bit) Bit complement : (M.bit) ~(M.bit) Bit OR C-flag : C C V (M.bit) Bit OR C-flag and NOT : C C V ~(M.bit) Set bit : (M.bit) "1" Set A.bit : (A.bit) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : (M.bit) C Test and clear bits with A : A - (M), (M) (M) ^ ~(A) Test and set bits with A : A - (M), (M) (M) V (A) FLAG NVGBHIZC -------C -------C MM - - - - Z ---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
A-10
Appendix A. GMS800 Series Instruction
5. Branch / Jump Operation
NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 MNENONIC BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp + X, rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL OP CODE y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F BYTE NO. 2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2 CYCLE NO 4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 U-page call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1, PCL (upage), PCH "OFFH" 24 TCALL n nA 1 8 Table call : M(SP) (PCH), SP SP -1, M(SP) (PCL), SP SP -1 PCL (Table vector L), PCH (Table vector H) --------------Branch if bit clear : if(bit) = 0, then PC PC + rel Branch if bit clear : if(bit) = 1, then PC PC + rel Branch if carry bit clear : if(C) = 0, then PC PC + rel Branch if carry bit set : If (C) =1, then PC PC + rel Branch if equal : if (Z) = 1, then PC PC + rel Branch if munus : if (N) = 1, then PC PC + rel Branch if not equal : if (Z) = 0, then PC PC + rel Branch if not minus : if (N) = 0, then PC PC + rel Branch always : PC PC + rel Branch if overflow bit clear : If (V) = 0, then PC PC + rel Branch if overflow bit set : If (V) = 1, then PC PC + rel Subroutine call M(SP) (PCH), SP SP-1, M(SP) (PCL), SPSP-1 if !abs, PC abs ; if [dp], PCL (dp), PCH (dp+1) Compare and branch if not equal ; If A (M), then PC PC + rel. Decrement and branch if not equal : if (M) 0, then PC PC + rel. Unconditional jump PC jump address ----------------------------OPERATION FLAG NVGBHIZC --------------MM - - - - Z ---------------------------------------------------------
A-11
Appendix A. GMS800 Series Instruction
6. Control Operation & etc.
NO. 1 MNENONIC BRK OP CODE 0F BYTE NO. 1 CYCLE NO 8 Software interrupt: B "1", M(SP) (PCH), SP SP - 1, M(s) (PCL), SP S - 1, M(SP) PSW, SP SP - 1, PCL (0FFDEH), PCH (0FFDFH) 2 3 4 5 6 7 8 9 10 11 12 13 14 DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET RETI 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F 7F 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 2 4 4 4 4 4 4 4 4 5 6 Return from subroutine : SP SP+1, PCL M(SP), SP SP+1, PCH M(SP) Return from interrupt : SP SP+1, PSW M(SP), SP SP+1,PCL M(SP), SP SP+1, PCH M(SP) 15 STOP EF 1 3 Stop mode (halt CPU, stop oscillator) -------(restored) -------Push to stack M(SP) Reg. SP SP - 1 -------(restored) Disable interrupts : I "0" Enable interrupts : I "1" No operation Pop from stack SP SP + 1, Reg. M(SP) ------------0------1-----------1-0-OPERATION FLAG NVGBHIZC
A-12
Appendix B. Programmer's guide
1. General Circuit Diagram of GMS81C50 series
VCC
1 2 3 4 5 6
R00 R01 R02 R03 R04 R05
R27 40 R26 39 R25 38 R24 37 R23 36 R22 35 R21 34 R20 33 R33 32 VSS 31 R32 30 R31 R30 29 28
Filter for Vcc-GND noise
220uF 0.1uF
GMS 81C50XX
7 R06
VCC
8 R07 9 R34 10 R35 11 VDD 12 R36
Infrared LED
Indicator LED
4MHz
OSC
13 R37 14 XOUT 15 XIN 16 R10 17 R11 18 R12
R17 27 R16 26 R40 25 REMOUT 24 R15 23 R14 22 RESET 21 0.1uF
vcc
TR1
19 R13 20 TEST
GND
R16
R15
R14
R13
R12
R10
R30
R23
R22
R21
R20
R17
121 113 105 122 114 106 123 115 107
124 116 108 100 125 117 109 101 126 118 110 102 127 119 111 103 128 120 112 104
R27
R26
R25
97 98 99
R24
89 81 90 82 91 83 92 84 93 85 94 86 95 87 96 88
73 74 75 76 77 78 79 80
65 66 67 68 69 70 71 72
57 58 59 60 61 62 63 64
49 50 51 52 53 54 55 56
41 42 43 44 45 46 47 48
33 25 34 26 35 27 36 28 37 29 38 30 39 31 40 32
17 18 19 20 21 22 23 24
9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
R00 R01 R02 R03 R04 R05 R06 R07
B-1
Appendix B. Programmer's guide
KEY MATRIX
= KEY
Figure B-1. Circuit Diagram
Note: Normally use the above 100uF capacitor for prevent power drop during pulse is transmitted. If you use the SRAM backup, use at least 220uF. We recommend to use ALKALINE battery.
Note: Figure B-1, Circuit Description: device : GMS81C5016 package : 40PIN PDIP port R0x : All input port with pull-up resistor port R1x : All output port with N-MOS Open drain port R11 : LED Drive port
B-2
Appendix B. Programmer's guide
2. Mask Option List Example Refer to Circuit B-1
GMS81C50 MASK OPTION LIST
Code Name : GMS81C5016 - Uxxx 1. Device & Package GMS81C5004 GMS81C5008 GMS81C5016 28PIN : SOP 40PIN : PDIP 44PIN : PLCC GMS81C5024 GMS81C5032 28 PIN : Skinny DIP 44PIN : MQFP LG Semicon Co., Ltd. M/L Application Team.
- R0 PORT
Port Y/N Y/N*3 R00 R01 R02 R03 R04
Y : Yes
R05 R06
N : No
R07
y y
R10
y y
R11
y y
R12
y y
R13
y y
R14
y y
Y : Yes
R15
y y
R16
y y
N : No
R17
- R1 PORT
Port Y/N Y/N*3
y y
R20
y y
R21
y y
R22
y y
R23
y y
R24
y y
Y : Yes
y y y y y y
y y
N : No
- R2 PORT
Port Y/N Y/N*3
R25 *2 R26 *2 R27 *2
y y y y
R40 *2
y y y y
Y : Yes
y y y y
y y y y
y y y y
y y
Y : Yes
y y
N : No
- R3 PORT
Port Y/N Y/N*3
R30 *2 R31 *2 R32 *2 R33 *2 R34 *2 R35 *2 R36 *2 R37 *2
y y
y y
- R4 PORT
Port Y/N Y/N*3
N : No
y y
< NOTICE > . *1 : is not available for 28PIN & 40PIN. So, Default option is Pull-Up. . *2 : is not available for 28PIN. So, Default Option is Pull-Up. . *3 : is for selecting Pull-up in LVD mode.
3. Low Voltage Detection (Means RAM retention) Y/N
Y
Date : Company Name : Section Name : Signature :
Note: Caution: When the power to the MCU would be decreased under LVD, all I/O ports are changed to input ports with pull up resistor. In below cases, you must take care of selecting the pull up in LVD.. You must detach the pull up of I/O port at thease cases. Case1 : When any I/O port is connected to GND, the cur-
rent will flow from the Pull up to GND. It cause the large power consumption and RAM would not be retained enough to satisfy your want. Case2 : The case of using any I/O port for controlling PNP TR., The TR is always turn on by the Pull up of I/O port in LVD mode
R00
< Case 1 >
Indicator LED
R00 PNP
< Case 2 >
B-3
Appendix B. Programmer's guide
3. Key Scan
To secure the key board scanning , read the input port after minimum 60uS delay time from output port set to Low . This time delay is for the port rising time depend on the input pull-up resistor . ; program example ,See the Figure B-1 circuit. ldm R1,#1111_1110b ;R10 port set to LOW call delay_60uS ;60uS time delay routine lda R0 ;R0 port Read
R0 port Read timing
R10 R11
60uS 60uS
< Fig B-2 , Input with pull-up port read time method >
* Current Consumption The current consumption during the Pulse transmission depends on the external circuit and each Protocol. Normally , if you used Fig B-1 circuit., the operation current is 15mA ~ 25mA (Max 45mA). But this value is normal case. Some special protocol can be possible to consume more larger current.
B-4

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